Power consumption of electric devices has become a critical metric along with traditional performance metrics, both for data center and consumer markets. In data centers, it is well known that the cooling cost can take up to one third of the total operating cost, so power consumption cannot be a low priority consideration any more. In addition to this, modern data center servers are adopting high performance solid-state drives (SSDs), such as nonvolatile memory (NVM) Express or NVMe compliant devices. NVMe is a specification for accessing solid-state drives (SSDs) attached through the PCI Express (PCIe) bus. An NVMe device commonly comes with high-performance CPUs and large dynamic random-access memories (e.g., DRAMs) to provide higher performance compared to other SSDs. Such high-performance devices can easily consume 25 W, which is a significant amount of power consumption, even in the data center configuration considering that commodity servers are commonly equipped with 8-16 such SSDs. Moreover, energy proportionality—that is, for low utilization of a given device, proportionally low power consumption, is expected. The same principle is directly applicable to consumer markets. Consumer mobile devices, such as laptops, are adopting high performance SSDs, such as PCIe-based SSDs. As such, power consumption of SSDs should be minimal when not in use. To do so, such SSDs should provide power-consumption control features.
Modern SSDs commonly come with performance throttling features, lowering its performance to reduce power consumption, mainly to protect itself from exceeding a power threshold over an allowed power consumption, which is commonly referred to as thermal design power (TDP). Such a mechanism, however, is mainly designed to protect circuits from thermal or electric damages by getting too hot or flowing too much current, respectively. But, this feature is insufficient to accommodate dynamic power control.
Due to its small cell size, high density, low power and high endurance, modern SSDs commonly utilize NAND flash memory as storage media. NAND flash has asymmetric latency and power consumption characteristics.
To boost its performance, hide high latency in programming and erasing due to the asymmetric characteristics of NAND flash memory, many different-levels or types of parallelisms are used. For example, multiple micro-controllers or general processors exist in SSDs to implement a Flash File System to mimic hard disk drives. That is to say, multiple CPUs execute the SSD's firmware that commonly incorporates an FTL (Flash Translation Layer). FTL translates LBA (logical block address) to PBA (physical block address) while taking charges of bad block management, garbage collection, and wear leveling. Because modern FTLs are complicated and requires high computation, multiple CPUs are commonly used to parallelize its task and also to execute user commands simultaneously. A second type of parallelism can be found in DRAM memory. DRAM is much slower than processors, and thus, DRAM organization commonly utilizes parallelism in its organization. Multi-rank or channel is an example. Lastly, NAND media and its organization introduces its own parallelism, including multi-plane, interleave, and multi-channel operations.
Although such parallelism can be controlled either directly from a host or user, or self-controlled based on configuration tables that manufacturers preconfigure, to control average power consumption of SSDs, there is currently no mechanism to dynamically control power consumption during operation.
What is needed is a mechanism to control power consumption of SSDs utilizing dynamically configurable parallelism.